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| ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 1 of 19 1 - 888 - 824 - 4184 features form, fit and function compatible with the dec ? 21140af available in 144 pin pqfp package integrated ethernet controller with pci bus interface supports 10 mb/s and 10/100 mb/s network interface pcs and scrambler/descrambler circuitry on chip sup ports multiple pci features: - unlimited pci burst - pci read multiple - pci write and invalidate - pci read line - pci 5.0v and 3.3v environments multiple interrupt sources contains two independent 3k fifos to minimize external memory additions prov ides sleep or snooze low - power modes interfaces with microwire ? serial rom provides a jtag test port with boundary scan function complies with ieee 802.3, ansi 8802 - 3, and ethernet standards the ia21140af is a "plug - and - play" drop - in replacement for th e original ic. innov asic produces replacement ics using its miles tm , or managed ic lifetime extension system, cloning technology. this technology produces replacement ics far more complex than "emulation" while ensuring they are compatible with the origina l ic. miles tm captures the design of a clone so it can be produced even as silicon technology advances. miles tm also verifies the clone against the original ic so that even the "undocumented features" are duplicated. this data sheet documents all necess ary engineering information about the ia21140af including functional and i/o descriptions, electrical characteristics, and applicable timing. innov asic
ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 2 of 19 1 - 888 - 824 - 4184 package pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 101 102 103 104 105 106 107 108 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 1 2 9 1 3 0 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 1 3 6 1 3 7 1 3 8 1 3 9 1 4 0 1 4 1 1 4 2 1 4 3 1 4 4 ia21140af int_n rst_n vdd vss pci_clk vdd vss gnt_n req_n ad[31] ad[30] vss ad[29] ad[28] ad[27] vss ad[26] vdd ad[25] ad[24] c_be_n[3] idsel vss ad[23] ad[22] ad[21] ad[20] vdd ad[19] ad[18] vdd vss vss ad[17] ad[16] vss c_be_n[2] frame_n irdy_n trdy_n devsel_n stop_n perr_n serr_n par c_be_n[1] ad[15] vss vdd vss ad[14] ad[13] vss ad[12] ad[11] vdd ad[10] ad[9] vss ad[8] c_be_n[0] ad[7] ad[6] vss ad[5] ad[4] vdd ad[3] ad[2] vss ad[1] ad[0] vss vdd mii_mdc mii_mdio nc br_a[1] br_ce_n br_a[0] br_ad[7] vss vdd br_ad[6] br_ad[5] br_ad[4] br_ad[3] br_ad[2] br_ad[1] br_ad[0] vss gep[7] gep[6] gep[5] gep[4] vdd vss gep[3] gep[2] gep[1] gep[0] sr_cs sr_ck sr_di sr_do vdd vss vdd_clamp tdi tms tck srl_txen srl_tclk srl_txd srl_rxen srl_rxd srl_clsn mii_srl tdo srl_rclk sym_txd[4] vdd vss mii_sym_txen mii_sym_txd[3] mii_sym_txd[2] mii_sym_txd[1] mii_sym_txd[0] sym_link mii_sym_tclk rcv_match vdd vss sym_rxd[4] mii_sym_rxd[3] mii_sym_rxd[2] mii_sym_rxd[1] mii_sym_rxd[0] mii_sym_rclk mii_crs mii_clsn mii_dv mii_err sd ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 3 of 19 1 - 888 - 824 - 4184 description the innov asic ia21140af fast ethernet lan controller provides a direct interface connection to the pci (peripheral component interface) bus. it interfaces with the pci bus by using on - chip control and status registers (csr?s), and a shared cpu memory area. the memory is initialized once during setup to mini mize cpu overhead during normal operation. large receive and transmit fifo?s are contained on - chip so no additional on board memory is required. the ia21140af includes two on chip direct memory access (dma) controllers with programmable burst size providin g for low cpu utilization. a pci clock frequency from dc to 33 mhz (20 - 33 mhz for operational network interface) is supported. two network ports are supported. a serial standard 7 - wire 10 - mbps port (srl) and a media independent interface/symbol 10/100 - mbps port (mii/sym). the 10 mbps implements a direct interface to the external 10 mbps front - end decoder (endec). the 10/100 mbps port supports two modes. the first is a 100base - x physical coding sublayer (pcs). the second is a full implementation of the mii s tandard. the ia21140af functions in a full - duplex environment for either network port. ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 4 of 19 1 - 888 - 824 - 4184 system block diagram this block below illustrates the major functions of the ia21140af. pci interface boot rom port serial rom port general- purpose register board control signals boot rom/ external register serial rom pci 32 32 8 rx fifo tx fifo rxm txm 10 mb/s physical coding sublayer scrambler/ descrambler mii/sym interface serial interface 10 mb/s or 100 mb/s dma 32 32 32 16 16 4 4 4 1 1 4 ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 5 of 19 1 - 888 - 824 - 4184 i/o description the following section provides a functional description of the i/o pins on the ia21140af. name type description vdd p 3.3 volt input supply voltage. vdd_clamp p 5.0 volt reference for 5.0 volt signaling environments and 3.3 volt reference for 3.3 volt signaling environments. vss p ground pin ad[31:0] i /o the pci address and data lines are multiplexed on the same pci pins. during the first clock cycle of a transaction, the 32 bits contain an address and during subsequent clock cycles, they contain data. both read and write bursts are supported in master operation only. big or little indian byte ordering can be used. br_a[1:0] o address line bit 0 also carries in two consecutive address cycles (bits 16 and 17) in a 256kb configuration. bit 1 also latches the boot rom address and control lines via two exte rnal latches. br_ad[7:0] i/o in the first of two consecutive address cycles, these multiplexed lines contain the boot rom address bits [7:2], oe_n, and we_n. the second cycle contains boot rom address bits [15:8]. bits 7 through 0 contain data during the data cycle. these lines are used to carry data to and from the external register. br_ce_n o enable pin for the boot rom or an external register. pin has an internal 5 k o pull - up resistor. c_be_n[3:0] i/o bus command and byte enable are multiplexed on th e same pci pins. these bits provide the bus command during the address phase of the transaction. they provide the byte enable during the data phase. byte enable determines which byte lines carry valid data. bit 0 coincides with byte 0. bit 1 coincides with byte 1, etc. devsel_n i/o indicates that the driving device has decoded its address as the target of the current access. as an input, determines whether a device on the bus has been selected. frame_n i/o the ia21140af bus master asserts this signal to i ndicate the beginning and duration of a bus transaction access. data transfer continues while this signal is asserted. deasserting this signal indicates the transaction is in the final phase. gep[7:0] i/o these pins can be configured by software to perfor m either input or output functions for system specific applications. gnt_n i indicates to the ia21140af that access to the bus has been granted. idsel i used as a chip select by the host to indicate configuration read and write cycles. int_n o/d when on e of the appropriate bits in csr5 gets set, interrupt request gets asserted if the corresponding mask bit in csr7 is not set. if more than one interrupt bit in csr5 is set and all input bits are not cleared, interrupt request gets deasserted for one clock cycle. interrupt request gets deasserted by writing a ?1? into the appropriate csr5 bit. this pin must be pulled up by an external resistor. ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 6 of 19 1 - 888 - 824 - 4184 name type description irdy_n i/o when the ia21140af is the bus master, this signal is asserted during write operations indicating valid data is present on the 32 - bit ad bus. it is asserted during read operations to indicate the master is ready to accept data. it is asserted during a write to indicate that valid data is on the ad lines. a data phase is completed on any rising edge of the cl ock when both irdy_n and trdy_n are asserted. wait cycles are inserted until both these signals are asserted together. mii_clsn i when an external physical layer protocol (phy) device detects a collision, it asserts this signal. carrier sense mii_crs i t he phy sets this bit when the media is active. mii_dv i an external phy sets this bit when receive data is on the mii_sym_rxd lines and is cleared at the end of the packet. this signal is synchronized with mii_sym_rclk. mii_err i when a data decoding err or is detected by an external phy device, this pin gets set. it is synchronized to mii_sym_rclk and can be set for a minimum of one receive clock. it sets the cyclic redundancy check (crc) error bit in the receive descriptor (rdes0) when it is set during a packet reception. mii_mdc o goes to the phy devices as timing reference for the transfer of information on the mii_mdio signal. mii_mdio i/o transfers control information and status between the ia21140af and phy. mii_srl o set when the mii/sym port is selected. cleared when the srl port is selected. mii_sym_rclk i this clock, recovered by the phy, supports either the 25 mhz or 2.5 mhz receive clock. mii_sym_rxd[3:0] i when mii mode is selected, these four parallel data lines receive data that is drive n by external phy that attached the media. synchronized to the mii_sym_rclk signal. mii_sym_tclk i this 25 mhz or 2.5 mhz transmit clock is supplied by the external physical layer medium dependent device (pmd) and must always be active. mii_sym_txd[3:0] o these four parallel transmit data lines are synchronized and latched by the external phy on the rising edge of the mii_sym_tclk signal. mii_txen o this signal indicates a transmit to an external phy device. it reflects the transmit activity of the mac s ublayer when in the pcs mode (csr6[23]). nc o no connection pins par i/o even parity bit for the 32 - bit ad bus and the 4 - bit c_be_n lines. it is driven by the master for address and write data phases and driven by the target for read data phases. pci_cl k i timing of the pci related functions is based on this dc to 33 mhz clock. all bus signals except int_n and rst_n are sampled on the rising edge of this clock. perr_n i/o used for reporting data parity errors during all pci transactions except a special cycle. rcv_match o set when a received packet passes address recognition. req_n o request to the bus arbiter for the ia21140af to use the bus. rst_n i when asserted for at least 10 pci clock cycles, the ia21140af is reset to its initial state. pci out put pins are tristated and all pci o/d signals are left floating. sd i supplied by an external pmd device. ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 7 of 19 1 - 888 - 824 - 4184 name type description serr_n o/d reports errors other than parity. signal must be valid for at least one clock cycle. this pin pulled up by an external resistor. sr_ck o serial rom clock. sr_cs o serial rom chip - select pin pulled down by an internal 2 k o resistor. sr_di o serial rom data - in. sr_do i serial rom data - out pin pulled up by an internal 5 k o resistor. srl_clsn i indicates a collision occurrence on the et hernet cable to the ia21140af. asserted and deasserted asynchronously by the external endec with respect to the receive clock. srl_rclk i carries the recovered receive clock supplied by an external endec. may be inactive during idle periods. srl_rxd i ca rries the input receive data from the external endec. incoming data should be synchronous with receive clock (srl_rclk) signal. srl_rxen i set when receive data is present on the ethernet cable and cleared at the end of a frame. set and cleared asynchrono usly to the receive clock by the external endec. srl_tclk i carries the transmit clock supplied by an external endec. must be always active, even during reset. srl_txd o carries the serial output data from the ia21140af and is synchronized to transmit cl ock signal. srl_txen o signals an external endec that the ia21140af transmit is in progress. stop_n i/o the current target is requesting the bus master to stop the current transaction. sym_link o descrambler is locked to the input data signal. sym_rxd [4] i this signal and the four receive lines mii_sym_rxd[3:0], provide five parallel data lines in symbol form for use in pcs mode. data is driven by an external pmd device and is synchronized with respect to the mii_sym_rclk signal. sym_txd[4] o this si gnal and the four transmit lines mii_sym_txd[3:0], provide five parallel data lines in symbol form for use in pcs mode. data is synchronized on the rising edge of mii_sym_tclk. tck i during jtag test operations this clock shifts state information and test data into and out of the ia21140af. the pin should not be left unconnected. tdi i during jtag test operations this pin serially shifts test data and instruction into the ia21140af. the pin is pulled up by an internal 5 k o resistor and should not be left unconnected. tdo o during jtag test operations this pin serially shifts test data and instructions out of the ia21140af. tms i controls the state operation of jtag testing in the ia21140af. the pin is pulled up by an internal 5 k o resistor and should n ot be left unconnected. trdy_n i/o indicates the readiness of the target?s agent to complete the current data phase of the transaction. during reads, this signal indicates that valid data is present on ad lines. during writes, this signal indicates the t arget is ready to accept data. a data phase is completed on any clock when both irdy_n and trdy_n are set. ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 8 of 19 1 - 888 - 824 - 4184 ac/dc parameters dc characteristics absolute max ratings symbol parameter min max unit v dd supply voltage (3.3v) 3 3.6 v v dd supply voltage (5v) 4.75 5.25 v t a ambient temperature (commercial) 0 70 c t j junction temperature (commercial) 0 85 c storage temperature - 55 125 c cmos input specifications (3.0v < vdd < 3.6v; 0 c < t < 70 c) symbol parameter min max unit vil low level input voltage - 0.3*v dd v vih high level input voltage 0.7*v dd - v lil low level input current - - 1 m a iih high level input current - 1 m a iil input pull - up current - 27 - 75 m a iih input pull - down current 35 112 m a vt - schmitt negative threshold 0.2*v dd - v vt+ schmitt positive threshold - 0.8*v dd v vh schmitt hysteresis 0.8 - v ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 9 of 19 1 - 888 - 824 - 4184 ttl input specifications (3.0v < vdd < 3.6v; 0 c < t < 70 c) symbol parameter min max unit vil low level input voltage - 0.8 v vih high level input voltage 2 - v lil low level input current - - 1 m a iih high level input current - 1 m a iil input pull - up current - 27 - 75 m a iih input pull - down current 35 112 m a vt - schmitt negative threshold 0.7 - v vt+ schmitt positive threshold - 2.1 v vh schmitt hysteresis 0.4 - v output operating specifica tions (3.0v ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 11 of 19 1 - 888 - 824 - 4184 pci reset: timing diagram pci_clk pci_rst internal reset 10 pci_clk cycles 33 pci_clk cycles timing characteristics symbol parameter min max conditions trst pci_rst pulse width 10 * tcycle not applicable pci_clk active ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 12 of 19 1 - 888 - 824 - 4184 pci other signals: timing diagram clk output input tval (max) tval (min) vtest* ton toff th tsu note: vtest is 1.5 v in a 5.0 v signaling environment and is 0.4 * vdd_clamp in a 3.3 v signaling environment. timing characteristics symbol parameter min max unit tval clk - to - signal valid delay 2 11 ns ton float - to - active delay from clk 2 - ns toff active - to - float delay from clk - 28 ns tsu i nput signal valid setup time before clk 7 - ns th input signal hold time from clk 0 - ns ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 13 of 19 1 - 888 - 824 - 4184 mii/sym port timing waveforms: transmit: timing diagram trv tcc trh tch tcr tcl tcf mii_sym_tclk mii_sym_txd[3:0] mii_sym_txen timing characteristics symbol definition min* typ* max* units tcc mii_sym_tclk cycle time ( 50 ppm) - 40t - ns tch mii_sym_tclk high time 14t - 26t ns tcl mii_sym_tclk low time 14t - 26t ns tcr mii_sym_tclk rise time - 8 - ns tcf mii_sym_tclk fall time - 8 - ns trv mii_ tclk rise to mii_txen valid time or mii_sym_t clk rise to mii_sym_txd valid time - - 20 ns trh mii_txen hold after mii_tclk rise time 5 - - ns t = 1 for 100 mbps operation and t = 10 for 10 mbps operation. ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 14 of 19 1 - 888 - 824 - 4184 receive: timing diagram tts tcc tth tch tcr tcl tcf mii_sym_rclk mii_sym_rxd[3:0] mii_dv timing characteristics symbol d efinition min* typ* max* unit tcc mii_sym_rclk cycle time ( 50 ppm) - 40t - ns tch mii_sym_rclk high time 14t - 26t ns tcl mii_sym_rclk low time 14t - 26t ns tcr mii_sym_rclk rise time - 8 - ns tcf mii_sym_rclk fall time - 8 - ns tts mii_sym_rxd setu p (both rise and fall) to mii_sym_rclk rise time or mii_dv setup (both rise and fall) to mii_rclk rise time 8 - - ns tth mii_sym_rxd hold (both rise and fall) after mii_sym_rclk rise time or mii_dv hold (both rise and fall) after mii_rclk rise time. 10 - - ns * t = 1 for 100 mbps operation and t = 10 for 10 mbps operation. ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 15 of 19 1 - 888 - 824 - 4184 receive error: timing diagram mii_rclk sd tts tth timing characteristics symbol definition min max units tts mii_err setup (both rise and fall) to mii_rclk rise time 10 - ns tth mii_err hold (both rise and fall) after mii_rclk rise time. 10 26t ns collision and carrier sense: timing diagram mii_clsn mii_crs tclh timing characteristics symbol definition min max units tclh mii_crs, mii_clsn high time 20 - ns ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 16 of 19 1 - 888 - 824 - 4184 serial port timing waveforms: transmit: timing diagram srl_tclk srl_txd[3:0] srl_txen ttcl ttch ttcf ttcr ttcc ttdp ttdh ttep tteh timing characteristics symbol definition min max units ttcl srl_tclk low time 45 55 ns ttch srl_tclk high time 45 55 ns ttcr srl_tclk rise time - 8 ns t tcf srl_tclk fall time - 8 ns ttdp srl_tclk fall time to srl_txd valid - 26 ns ttdh srl_txd hold after srl_tclk fall time 5 - ns ttep srl_tclk fall time to srl_txen valid - 26 ns tteh srl_txen hold after srl_tclk fall time 5 - ns ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 17 of 19 1 - 888 - 824 - 4184 receive: timing diagram trcl trch trcr trcf trds trdh trcc srl_rclk srl_rxd srl_rxen srl_rclk srl_rxd srl_rxen treh trel start of packet end of packet bit n-1 bit n ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 18 of 19 1 - 888 - 824 - 4184 timing characteristics symbol definition min max units trcc srl_rclk cycle time 85 118 ns trcl srl_rclk low time 38 80 ns trch srl_rclk high time 38 80 ns trcr srl_rclk rise time - 8 ns trcf srl_rclk fall time - 8 ns trds srl_rxd setup to srl_rclk fall time 10 - ns trdh srl_rxd hold after srl_rclk fall time 5 - ns trel srl_rxen low time 120 - ns treh srl_rxen hold after srl_rclk rise time 10 100 ns collision: timing diagram tclh srl_clsn timing characteristics symbol definition min max units tclh srl_clsn high time 20 - ns ia21140af preliminary data sheet pci fast ethernet lan controller copyright ? 2001 eng210010110 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 19 of 19 1 - 888 - 824 - 4184 ordering information order number environment package type ia21140af - pqf144i industrial 144 pin plastic quad flat package cross reference to original manufacturer part numbers: innovasic part number dec part number ia21140af - pqf144i q 21140 - aa q 21140 - ae q 21140 - af |
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